Issued Patents 2011
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8037438 | Techniques for parallel buffer insertion | Zhuo Li, Damir A. Jamsek, Chin Ngai Sze, Ying Zhou | 2011-10-11 |
| 8015532 | Optimal timing-driven cloning under linear delay model | Zhuo Li, David A. Papa, Chin Ngai Sze | 2011-09-06 |
| 8010926 | Clock power minimization with regular physical placement of clock repeater components | Ruchir Puri, Shyam Ramji, Ashish Singh, Chin Ngai Sze | 2011-08-30 |
| 7934188 | Legalization of VLSI circuit placement with blockages using hierarchical row slicing | Michael W. Dotson, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan | 2011-04-26 |
| 7895557 | Concurrent buffering and layer assignment in integrated circuit layout | Zhuo Li, Tuhin Mahmud, Stephen T. Quay, Paul G. Villarrubla | 2011-02-22 |
| 7890905 | Slew constrained minimum cost buffering | Arvind K. Karandikar, Tuhin Mahmud, Stephen T. Quay, Chin Ngai Sze | 2011-02-15 |
| 7882475 | Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors | Gi-Joon Nam, Haoxing Ren, Paul G. Villarrubia, Natarajan Viswanathan | 2011-02-01 |