Issued Patents 2011
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8051403 | Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus | Yasuyuki Nozuyama | 2011-11-01 |
| 7952390 | Logic circuit having gated clock buffer | Shuji Hamada | 2011-05-31 |