JP

Joel R. Phillips

CS Cadence Design Systems: 2 patents #27 of 259Top 15%
📍 San Jose, CA: #856 of 4,297 inventorsTop 20%
🗺 California: #7,487 of 41,698 inventorsTop 20%
Overall (2011): #89,880 of 364,097Top 25%
2
Patents 2011

Issued Patents 2011

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7996193 Method for reducing model order exploiting sparsity in electronic design automation and analysis Zuochang Ye, Zhenhai Zhu 2011-08-09
7882471 Timing and signal integrity analysis of integrated circuits with semiconductor process variations Vinod Kariat, Igor Keller 2011-02-01