DG

Dinesh Gupta

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 Princeton Junction, NJ: #17 of 43 inventorsTop 40%
🗺 New Jersey: #1,952 of 6,350 inventorsTop 35%
Overall (2011): #315,778 of 364,097Top 90%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7926011 System and method of generating hierarchical block-level timing constraints from chip-level timing constraints Oleg Levitsky, Chien-Chu Kuo 2011-04-12