CK

Chien-Chu Kuo

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 San Jose, CA: #1,637 of 4,297 inventorsTop 40%
🗺 California: #14,783 of 41,698 inventorsTop 40%
Overall (2011): #333,418 of 364,097Top 95%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7926011 System and method of generating hierarchical block-level timing constraints from chip-level timing constraints Oleg Levitsky, Dinesh Gupta 2011-04-12