Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6975980 | Hierarchical linking module connection to access ports of embedded cores | — | 2005-12-13 |
| 6963225 | Quad state logic design methods, circuits, and systems | — | 2005-11-08 |
| 6959408 | IC with serial scan path, protocol memory, and event circuit | — | 2005-10-25 |
| 6954080 | Method and apparatus for die testing on wafer | — | 2005-10-11 |
| 6944247 | Plural circuit selection using role reversing control inputs | — | 2005-09-13 |
| 6898749 | IC with cache bit memory in series with scan segment | Joel J. Graber | 2005-05-24 |
| 6898544 | Instruction register and access port gated clock for scan cells | — | 2005-05-24 |
| 6894308 | IC with comparator receiving expected and mask data from pads | Alan Hales | 2005-05-17 |
| 6877122 | Link instruction register providing test control signals to core wrappers | — | 2005-04-05 |