Issued Patents 2005
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6944582 | Methods for reducing bitline voltage offsets in memory devices | — | 2005-09-13 |
| 6934213 | Method and apparatus for reducing write power consumption in random access memories | — | 2005-08-23 |
| 6924687 | Voltage tolerant circuit for protecting an input buffer | Brian Reed, Puneet Sawhney, Jayanth Thyamagundlam | 2005-08-02 |
| 6915251 | Memories having reduced bitline voltage offsets | — | 2005-07-05 |
| 6865119 | Negatively charged wordline for reduced subthreshold current | — | 2005-03-08 |