WN

William C. Naylor

SY Synopsys: 2 patents #5 of 58Top 9%
📍 San Jose, CA: #418 of 2,758 inventorsTop 20%
🗺 California: #3,616 of 26,868 inventorsTop 15%
Overall (2005): #29,289 of 245,428Top 15%
2
Patents 2005

Issued Patents 2005

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6951003 Placing cells of an IC design using partition preconditioning Troy W. Barbee, III, Ross A. Donelly 2005-09-27
6948143 Constrained optimization with linear constraints to remove overlap among cells of an integrated circuit Ross A. Donelly, Jason R. Woolever 2005-09-20