Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6965906 | Converting negative floating point numbers to integer notation without two's complement hardware | — | 2005-11-15 |
| 6954912 | Error detection in dynamic logic circuits | Pranjal Srivastava, Ajay Naini | 2005-10-11 |