Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6965987 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl Senter Brashears, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg +4 more | 2005-11-15 |
| 6959375 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara +3 more | 2005-10-25 |
| 6957320 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl D. Senter | 2005-10-18 |
| 6954847 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Yoshiyuki Miyayama, Le Trong Nguyen | 2005-10-11 |
| 6948052 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara +3 more | 2005-09-20 |
| 6941447 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara +3 more | 2005-09-06 |
| 6934829 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara +3 more | 2005-08-23 |
| 6920548 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor | Sanjiv Garg, Trevor Deosaran | 2005-07-19 |
| 6915412 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara +3 more | 2005-07-05 |