Issued Patents 2005
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6975555 | Magnetic random access memory using memory cells with rotated magnetic storage elements | Yu Lu, William Robert Reohr | 2005-12-13 |
| 6965527 | Multibank memory on a die | Luca Fasoli | 2005-11-15 |
| 6963504 | Apparatus and method for disturb-free programming of passive element memory cells | N. Johan Knall | 2005-11-08 |
| 6960794 | Formation of thin channels for TFT devices to ensure low variability of threshold voltages | Andrew J. Walker, S. Brad Herner, Maitreyee Mahajani, En-Hsing Chen, Sucheta Nallamothu +1 more | 2005-11-01 |
| 6954394 | Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions | N. Johan Knall, James M. Cleeves, Bendik Kleveland, Mark G. Johnson | 2005-10-11 |
| 6940109 | High density 3d rail stack arrays and method of making | Kedar Patel, Alper Ilkbahar, Andrew J. Walker | 2005-09-06 |
| 6937495 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics | — | 2005-08-30 |
| 6928590 | Memory device and method for storing bits in non-adjacent storage locations in a memory array | Alper Ilkbahar, Derek Bosch | 2005-08-09 |
| 6895490 | Method for making a write-once memory device read compatible with a write-many file system | Christopher S. Moore, Richard M. Fruin, Colm P. Lysaght | 2005-05-17 |
| 6894936 | Memory device and method for selectable sub-array activation | Bendik Kleveland | 2005-05-17 |
| 6889307 | Integrated circuit incorporating dual organization memory array | — | 2005-05-03 |
| 6879505 | Word line arrangement having multi-layer word line segments for three-dimensional memory array | — | 2005-04-12 |
| 6868022 | Redundant memory structure using bad bit pointers | Mark G. Johnson, Derek Bosch, Alper Ilkbahar, J. James Tringali | 2005-03-15 |
| 6859410 | Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch | Matthew P. Crowley | 2005-02-22 |
| 6856572 | Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device | Matthew P. Crowley | 2005-02-15 |
| 6849905 | Semiconductor device with localized charge storage dielectric and method of making same | Alper Ilkbahar, Andrew J. Walker, Luca Fasoli | 2005-02-01 |