Issued Patents 2005
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6954209 | Computer CPU and memory to accelerated graphics port bridge having a plurality of physical buses with a single logical bus number | — | 2005-10-11 |
| 6925578 | Fault-tolerant switch architecture | An H. Lam | 2005-08-02 |
| 6898740 | Computer system having configurable core logic chipset for connection to a fault-tolerant accelerated graphics port bus and peripheral component interconnect bus | — | 2005-05-24 |
| 6895456 | System supporting multicast master cycles between different busses in a computer system | Thomas J. Bonola, Ramkrishna Prakash | 2005-05-17 |
| 6886109 | Method and apparatus for expediting system initialization | Michael F. Angelo, Chai S. Heng | 2005-04-26 |
| 6886065 | Improving signal integrity in differential signal systems | Chi Kim Sides | 2005-04-26 |
| 6865647 | Dynamic cache partitioning | Phillip M. Jones, John E. Jenne | 2005-03-08 |
| 6862646 | Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain | Thomas J. Bonola, John E. Larson | 2005-03-01 |