Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6961843 | Method frame storage using multiple memory circuits | James M. O'Connor | 2005-11-01 |
| 6950923 | Method frame storage using multiple memory circuits | James M. O'Connor | 2005-09-27 |
| 6944724 | Method and apparatus for decoupling tag and data accesses in a cache memory | Shailender Chaudhry | 2005-09-13 |
| 6938130 | Method and apparatus for delaying interfering accesses from other threads during transactional program execution | Quinn A. Jacobson, Shailender Chaudhry | 2005-08-30 |
| 6938147 | Processor with multiple-thread, vertically-threaded pipeline | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2005-08-30 |
| 6934809 | Automatic prefetch of pointers | Shailender Chaudhry | 2005-08-23 |
| 6862664 | Method and apparatus for avoiding locks by speculatively executing critical sections | Shailender Chaudhry, Quinn A. Jacobson | 2005-03-01 |
| 6862693 | Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step | Shailender Chaudhry | 2005-03-01 |
| 6848071 | Method and apparatus for updating an error-correcting code during a partial line store | Shailender Chaudhry | 2005-01-25 |