Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6965985 | Sign generation bypass path to aligner for reducing signed data load latency | David M. Pini, Anup S. Tirumala | 2005-11-15 |
| 6865098 | Row redundancy in a content addressable memory device | Michael E. Ichiriu, Masaru Shinohara, Lan Lee | 2005-03-08 |