Issued Patents 2005
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6980042 | Delay line synchronizer apparatus and method | — | 2005-12-27 |
| 6910088 | Bus arbitration using monitored windows of time | — | 2005-06-21 |
| 6898648 | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing | — | 2005-05-24 |
| 6888760 | System and method for multiplexing data and data masking information on a data bus of a memory device | — | 2005-05-03 |
| 6880094 | Cas latency select utilizing multilevel signaling | — | 2005-04-12 |
| 6876589 | Method and apparatus for supplementary command bus | — | 2005-04-05 |
| 6851032 | Latency reduction using negative clock edge and read flags | Jeff Janzen | 2005-02-01 |