Issued Patents 2005
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6950487 | Phase splitter using digital delay locked loops | R. Jacob Baker | 2005-09-27 |
| 6940328 | Methods and apparatus for duty cycle control | — | 2005-09-06 |
| 6930955 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brian Johnson, Brent Keeth | 2005-08-16 |
| 6930525 | Methods and apparatus for delay circuit | Tyler Gomm | 2005-08-16 |
| 6912666 | Interleaved delay line for phase locked and delay locked loops | — | 2005-06-28 |
| 6895522 | Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock | James B. Johnson | 2005-05-17 |
| 6891415 | Method and apparatus for enabling a timing synchronization circuit | Vladimir Mikhalev | 2005-05-10 |
| 6868504 | Interleaved delay line for phase locked and delay locked loops | — | 2005-03-15 |
| 6845459 | System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines | — | 2005-01-18 |
| 6845458 | System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines | — | 2005-01-18 |
| 6839301 | Method and apparatus for improving stability and lock time for synchronous circuits | J. Brian Johnson | 2005-01-04 |