Issued Patents 2005
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979880 | Scalable high performance antifuse structure and process | Joseph E. Geusic | 2005-12-27 |
| 6958263 | Methods of forming devices, constructions and systems comprising thyristors | — | 2005-10-25 |
| 6955960 | Decoupling capacitor for high frequency noise immunity | — | 2005-10-18 |
| 6950340 | Asymmetric band-gap engineered nonvolatile memory device | — | 2005-09-27 |
| 6943065 | Scalable high performance antifuse structure and process | Joseph E. Geusic | 2005-09-13 |
| 6933572 | Field-shielded SOI-MOS structure free from floating body effect, and method of fabrication therefor | — | 2005-08-23 |
| 6917078 | One transistor SOI non-volatile random access memory cell | — | 2005-07-12 |
| 6908798 | Methods of making semiconductor-on-insulator thin film transistor constructions | — | 2005-06-21 |
| 6903969 | One-device non-volatile random access memory cell | — | 2005-06-07 |
| 6903001 | Techniques to create low K ILD for BEOL | Paul A. Farrar | 2005-06-07 |
| 6900667 | Logic constructions and electronic devices | — | 2005-05-31 |
| 6888200 | One transistor SOI non-volatile random access memory cell | — | 2005-05-03 |
| 6882010 | High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters | — | 2005-04-19 |
| 6873015 | Semiconductor constructions comprising three-dimensional thin film transistor devices and resistors | — | 2005-03-29 |
| 6873018 | Memory cell constructions comprising integrated bipolar and FET devices | — | 2005-03-29 |
| 6845034 | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons | — | 2005-01-18 |