Issued Patents 2005
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974735 | Dual layer Semiconductor Devices | — | 2005-12-13 |
| 6969875 | Buried channel strained silicon FET using a supply layer created through ion implantation | — | 2005-11-29 |
| 6940089 | Semiconductor device structure | Zhiyuan Cheng, Dimitri Antoniadis | 2005-09-06 |
| 6927147 | Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates | Arthuer J. Pitera | 2005-08-09 |
| 6921914 | Process for producing semiconductor article using graded epitaxial growth | Zhi-Yuan Cheng, Dimitri Antoniadis, Judy L. Hoyt | 2005-07-26 |
| 6916727 | Enhancement of P-type metal-oxide-semiconductor field effect transistors | Christopher Leitz, Minjoo L. Lee | 2005-07-12 |
| 6900103 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits | — | 2005-05-31 |
| 6881632 | Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS | Nicole Gerrish | 2005-04-19 |
| 6876010 | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization | — | 2005-04-05 |
| 6864115 | Low threading dislocation density relaxed mismatched epilayers without high temperature growth | — | 2005-03-08 |
| 6846715 | Gate technology for strained surface channel and strained buried channel MOSFET devices | Richard Hammond, Matthew T. Currie | 2005-01-25 |
| 6838728 | Buried-channel devices and substrates for fabrication of semiconductor-based devices | Anthony J. Lochtefeld | 2005-01-04 |