Issued Patents 2005
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6975005 | Current reference apparatus and systems | Siva G. Narendra, Stephen H. Tang, Zachary Keer | 2005-12-13 |
| 6970018 | Clocked cycle latch circuit | Dejan Markovic, James W. Tschanz | 2005-11-29 |
| 6952376 | Method and apparatus to generate a reference value in a memory array | Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang +2 more | 2005-10-04 |
| 6917237 | Temperature dependent regulation of threshold voltage | James W. Tschanz, Mircea R. Stan, Siva G. Narendra | 2005-07-12 |
| 6909652 | SRAM bit-line reduction | Yibin Ye, Dinesh Somasekhar, Muhammad M. Khellah | 2005-06-21 |
| 6906973 | Bit-line droop reduction | Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang +2 more | 2005-06-14 |
| 6903984 | Floating-body DRAM using write word line for increased retention time | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +1 more | 2005-06-07 |
| 6879531 | Reduced read delay for single-ended sensing | Dinesh Somasekhar, Yibin Ye, Fatih Hamzaoglu | 2005-04-12 |
| 6876571 | Static random access memory having leakage reduction circuit | Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye | 2005-04-05 |
| 6870418 | Temperature and/or process independent current generation circuit | Stephen H. Tang, Siva G. Narendra | 2005-03-22 |
| 6849909 | Method and apparatus for weak inversion mode MOS decoupling capacitor | Rajendran Nair, Siva G. Narendra, Tanay Karnik | 2005-02-01 |