Issued Patents 2005
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6976129 | Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture | Kenneth C. Creta, Manoj Khare, Akhilesh Kumar | 2005-12-13 |
| 6971098 | Method and apparatus for managing transaction requests in a multi-node architecture | Manoj Khare, Akhilesh Kumar, Ioannis T. Schoinas | 2005-11-29 |
| 6859864 | Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line | Manoj Khare, Akhilesh Kumar, Kenneth C. Creta | 2005-02-22 |
| 6842830 | Mechanism for handling explicit writeback in a cache coherent multi-node architecture | Manoj Khare, Akhilesh Kumar | 2005-01-11 |