Issued Patents 2005
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6954098 | Power-rail ESD clamp circuit for mixed-voltage I/O buffer | Kuo-Chun Hsu | 2005-10-11 |
| 6933573 | Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof | Kei-Kang Hung, Tien-Hao Tang | 2005-08-23 |
| 6927602 | Mixed-voltage CMOS I/O buffer with thin oxide device and dynamic n-well bias circuit | Chia-Sheng Tsai, Che-Hao Chuang | 2005-08-09 |
| 6920026 | ESD protection circuit with whole-chip ESD protection | Zi-Ping Chen, Chyh-Yih Chang | 2005-07-19 |
| 6912109 | Power-rail ESD clamp circuits with well-triggered PMOS | Mau-Lin Wu | 2005-06-28 |
| 6903913 | ESD protection circuit for mixed-voltage I/O ports using substrated triggering | Chien-Hui Chuan | 2005-06-07 |
| 6894324 | Silicon-on-insulator diodes and ESD protection circuits | Kei-Kang Hung, Tien-Hao Tang | 2005-05-17 |
| 6885529 | CDM ESD protection design using deep N-well structure | Hun-Hsien Chang, Wen-Tai Wang | 2005-04-26 |
| 6885179 | Low-voltage bandgap reference | Ching-Yun Chu, Wen-Yu Lo | 2005-04-26 |
| 6885534 | Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks | Cheng-Ming Lee, Wen-Yu Lo | 2005-04-26 |
| 6882009 | Electrostatic discharge protection device and method of manufacturing the same | Tang-Kui Tseng, Hsin-Chin Jiang, Chyh-Yih Chang, Jeng-Jie Peng | 2005-04-19 |
| 6867957 | Stacked-NMOS-triggered SCR device for ESD-protection | Paul C. F. Tong, Ping Ping Xu | 2005-03-15 |
| 6867461 | ESD protection circuit | Kun-Hsien Lin | 2005-03-15 |
| 6861680 | Silicon-on-insulator diodes and ESD protection circuits | Kei-Kang Hung, Tien-Hao Tang | 2005-03-01 |
| 6858901 | ESD protection circuit with high substrate-triggering efficiency | Kuo-Chun Hsu | 2005-02-22 |
| 6838734 | ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications | Tung-Yang Chen, Hun-Hsien Chang | 2005-01-04 |
| 6838908 | Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits | Che-Hao Chuang, Kuo-Chung Lee, Hsin-Chin Jiang | 2005-01-04 |