Issued Patents 2005
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6967885 | Concurrent refresh mode with distributed row address counters in an embedded DRAM | John E. Barth, Jr., Paul C. Parries | 2005-11-22 |
| 6954387 | Dynamic random access memory with smart refresh scheduler | Hoki Kim, David R. Hanson, Gregory J. Fredeman, John W. Golz | 2005-10-11 |
| 6950353 | Cell data margin test with dummy cell | Hoki Kim | 2005-09-27 |
| 6948028 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Chorng-Lii Hwang, Seiji Munetoh | 2005-09-20 |
| 6947348 | Gain cell memory having read cycle interlock | Hoki Kim | 2005-09-20 |
| 6845033 | Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology | John W. Golz | 2005-01-18 |
| 6845059 | High performance gain cell architecture | Matthew R. Wordeman, John E. Barth, Jr. | 2005-01-18 |