Issued Patents 2005
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6948146 | Simplified tiling pattern method | Robert J. Allen, John M. Cohn, Peter A. Habitz, William C. Leipold, Ivan L. Wemple | 2005-09-20 |
| 6883152 | Voltage island chip implementation | Thomas R. Bednar, Scott Whitney Gould, David E. Lackey, Douglas W. Stout | 2005-04-19 |
| 6883155 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Scott Whitney Gould, Jeannie H. Panner | 2005-04-19 |