Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6961276 | Random access memory having an adaptable latency | Francois Ibrahim Atallah, James Norris Dieffenderfer, Jeffrey Herbert Fischer, Michael T. Fragano, Daniel Stephen Geise +5 more | 2005-11-01 |
| 6944075 | Variable column redundancy region boundaries in SRAM | Steven M. Eustis, Michael T. Fragano | 2005-09-13 |
| 6928377 | Self-test architecture to implement data column redundancy in a RAM | Steven M. Eustis, Krishnendu Mondal, Jeremy Rowland | 2005-08-09 |
| 6922649 | Multiple on-chip test runs and repairs for memories | Krishnendu Mondal | 2005-07-26 |
| 6920525 | Method and apparatus of local word-line redundancy in CAM | Thomas Chadwick, Tarl S. Gordon, Rahul K. Nadkarni, Jeremy Rowland | 2005-07-19 |
| 6856569 | Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability | Erik A. Nelson | 2005-02-15 |