Issued Patents 2005
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6978361 | Effectively infinite branch prediction table mechanism | — | 2005-12-20 |
| 6963988 | Fixed point unit power reduction mechanism for superscalar loop execution | — | 2005-11-08 |
| 6963964 | Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses | — | 2005-11-08 |
| 6941421 | Zero delay data cache effective address generation | — | 2005-09-06 |
| 6934831 | Power reduction mechanism for floating point register file reads | — | 2005-08-23 |
| 6922714 | Floating point unit power reduction scheme | — | 2005-07-26 |
| 6922767 | System for allowing only a partial value prediction field/cache size | Richard J. Eickemeyer | 2005-07-26 |
| 6912649 | Scheme to encode predicted values into an instruction stream/cache without additional bits/area | — | 2005-06-28 |
| 6910104 | Icache-based value prediction mechanism | — | 2005-06-21 |
| 6901504 | Result forwarding of either input operand to same operand input to reduce forwarding path | — | 2005-05-31 |
| 6877069 | History-based carry predictor for data cache address generation | — | 2005-04-05 |
| 6868489 | Carry generation in address calculation | — | 2005-03-15 |
| 6868033 | Dual array read port functionality from a one port SRAM | Anthony Gus Aipperspach | 2005-03-15 |