Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979606 | Use of silicon block process step to camouflage a false transistor | Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison | 2005-12-27 |
| 6940764 | Memory with a bit line block and/or a word line block for preventing reverse engineering | William M. Clark, Jr., Lap-Wai Chow | 2005-09-06 |
| 6924552 | Multilayered integrated circuit with extraneous conductive traces | Lap-Wai Chow, William M. Clark, Jr., Paul Ou Yang | 2005-08-02 |
| 6919600 | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact | Lap-Wai Chow, William M. Clark, Jr. | 2005-07-19 |
| 6897535 | Integrated circuit with reverse engineering protection | Lap-Wai Chow, William M. Clark, Jr. | 2005-05-24 |
| 6893916 | Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same | Lap-Wai Chow, William M. Clark, Jr. | 2005-05-17 |