TT

Tsuneo Terasawa

RT Renesas Technology: 1 patents #364 of 1,110Top 35%
📍 Yokohama, WA: #14 of 17 inventorsTop 85%
Overall (2005): #82,381 of 245,428Top 35%
1
Patents 2005

Issued Patents 2005

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6849540 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF PRODUCING A MULTI-CHIP MODULE THAT INCLUDES PATTERNING WITH A PHOTOMASK THAT USES METAL FOR BLOCKING EXPOSURE LIGHT AND A PHOTOMASK THAT USES ORGANIC RESIN FOR BLOCKING EXPOSURE LIGHT Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori 2005-02-01