Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979885 | Devices with patterned wells and method for forming same | — | 2005-12-27 |
| 6979624 | Reduced mask count buried layer process | — | 2005-12-27 |
| 6974753 | Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions | — | 2005-12-13 |
| 6946364 | Integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, Dustin A. Woodbury | 2005-09-20 |
| 6946720 | Bipolar transistor for an integrated circuit having variable value emitter ballast resistors | — | 2005-09-20 |
| 6902967 | Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action | — | 2005-06-07 |
| 6897103 | MOS integrated circuit with reduced on resistance | — | 2005-05-24 |
| 6894349 | Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide | — | 2005-05-17 |
| 6867495 | Integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, Dustin A. Woodbury | 2005-03-15 |