Issued Patents 2005
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6919236 | Biased, triple-well fully depleted SOI structure, and various methods of making and operating same | Derick J. Wristers, Mark B. Fuselier | 2005-07-19 |
| 6884702 | Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate | Derick J. Wristers, Mark B. Fuselier | 2005-04-26 |
| 6876037 | Fully-depleted SOI device | Derick J. Wristers, Mark B. Fuselier | 2005-04-05 |
| 6864516 | SOI MOSFET junction degradation using multiple buried amorphous layers | Akif Sultan, David Wu | 2005-03-08 |