Issued Patents 2005
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6940356 | Circuitry to reduce PLL lock acquisition time | James J. McDonald, II | 2005-09-06 |
| 6927460 | Method and structure for BiCMOS isolated NMOS transistor | Steven Leibiger, Michael Harley-Stead, Daniel Hahn | 2005-08-09 |
| 6894553 | Capacitively coupled current boost circuitry for integrated voltage regulator | James J. McDonald, II | 2005-05-17 |
| 6855964 | Triggering of an ESD NMOS through the use of an N-type buried layer | — | 2005-02-15 |