Issued Patents 2005
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6970030 | Dual phased-locked loop structure having configurable intermediate frequency and reduced susceptibility to interference | Yunteng Huang, Ligang Zhang | 2005-11-29 |
| 6937046 | Non-invasive, low pin count test circuits and methods | Murari Kejariwal, Prasad Ammisetti, John L. Melanson | 2005-08-30 |
| 6891430 | Techniques for signal measurement using a conditionally stable amplifier | Edwin De Angel, Sherry Wu, Lei Wang, Aryesh Amar | 2005-05-10 |
| 6885211 | Internal node offset voltage test circuits and methods | Sherry X. Wu, Murari Kejariwal, Ammisetti Prasad, John L. Melanson | 2005-04-26 |
| 6857002 | Integrated circuit with a mode control selecting settled and unsettled output from a filter | Jerome E. Johnston, Edwin De Angel, Aryesh Amar | 2005-02-15 |