MP

Manish Pandey

CS Cadence Design Systems: 1 patents #18 of 77Top 25%
📍 Saratoga, CA: #143 of 352 inventorsTop 45%
🗺 California: #7,981 of 26,868 inventorsTop 30%
Overall (2005): #143,112 of 245,428Top 60%
1
Patents 2005

Issued Patents 2005

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6848084 Method and apparatus for verification of memories at multiple abstraction levels Mitchell Hines, Chih-Chang Lin 2005-01-25