Issued Patents 2005
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6976204 | Circuit and method for correcting erroneous data in memory for pipelined reads | James R. Magro, Dan S. Mudgett | 2005-12-13 |
| 6968417 | Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system | Tahsin Askar | 2005-11-22 |
| 6883045 | Apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system | Tahsin Askar | 2005-04-19 |