Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6784539 | Thermally enhanced semiconductor chip having integrated bonds over active circuits | — | 2004-08-31 |
| 6784493 | Line self protecting multiple output power IC architecture | David Alexander Grant, Ramanathan Ramani, Dale J. Skelton, David D. Briggs, Chin-Yu Tsai | 2004-08-31 |
| 6770935 | Array of transistors with low voltage collector protection | David Alexander Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale J. Skelton | 2004-08-03 |
| 6753575 | Tank-isolated-drain-extended power device | Chin-Yu Tsai | 2004-06-22 |
| 6729886 | Method of fabricating a drain isolated LDMOS device | Chin-Yu Tsai | 2004-05-04 |
| 6710427 | Distributed power device with dual function minority carrier reduction | David Alexander Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale J. Skelton | 2004-03-23 |
| 6709900 | Method of fabricating integrated system on a chip protection circuit | David Alexander Grant, Ramanathan Ramani, Dale J. Skelton, David D. Briggs, Chin-Yu Tsai | 2004-03-23 |
| 6683380 | Integrated circuit with bonding layer over active circuitry | Donald C. Abbott, Walter Bucksch, Marco Corsi, Chi-Cheong Shen, John P. Erdeljac +5 more | 2004-01-27 |
| 6680226 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology | Alec J. Morton, Chin-Yu Tsai | 2004-01-20 |