Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812576 | Fanned out interconnect via structure for electronic package substrates | Mark Patterson | 2004-11-02 |
| 6781229 | Method for integrating passives on-die utilizing under bump metal and related structure | — | 2004-08-24 |
| 6762494 | Electronic package substrate with an upper dielectric layer covering high speed signal traces | Jean-Marc Papillon, Steven J. Martin | 2004-07-13 |
| 6713853 | Electronic package with offset reference plane cutout | Michel Fleury, Mark Patterson | 2004-03-30 |
| 6674174 | Controlled impedance transmission lines in a redistribution layer | Surasit Chungpaiboonpatana, Hassan S. Hashemi | 2004-01-06 |
| 6674646 | Voltage regulation for semiconductor dies and related structure | Khosrow Golshan, Hassan S. Hashemi | 2004-01-06 |