Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822297 | Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness | Mahalingam Nandakumar, Song Zhao | 2004-11-23 |
| 6794730 | High performance PNP bipolar device fully compatible with CMOS process | Shaoping Tang, Seetharaman Sridhar, Amitava Chatterjee | 2004-09-21 |
| 6773972 | Memory cell with transistors having relatively high threshold voltages in response to selective gate doping | Andrew Marshall, David B. Scott, Douglas E. Mercer | 2004-08-10 |
| 6767810 | Method to increase substrate potential in MOS transistors used in ESD protection circuits | Craig T. Salling, Amitava Chatterjee | 2004-07-27 |
| 6730555 | Transistors having selectively doped channel regions | Amitava Chatterjee | 2004-05-04 |
| 6723616 | Process of increasing screen dielectric thickness | Seetharaman Sridhar, Zhiqiang Wu, Mark S. Rodder | 2004-04-20 |
| 6713334 | Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask | Mahalingam Nandakumar, Amitava Chatterjee | 2004-03-30 |