Issued Patents 2004
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6772321 | Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor | Marc Tremblay | 2004-08-03 |
| 6754775 | Method and apparatus for facilitating flow control during accesses to cache memory | Marc Tremblay | 2004-06-22 |
| 6732363 | Supporting inter-process communication through a conditional trap instruction | Marc Tremblay | 2004-05-04 |
| 6718839 | Method and apparatus for facilitating speculative loads in a multiprocessor system | Marc Tremblay | 2004-04-13 |
| 6721855 | Using an L2 directory to facilitate speculative loads in a multiprocessor system | Marc Tremblay | 2004-04-13 |
| 6721944 | Marking memory elements based upon usage of accessed information during speculative execution | Marc Tremblay | 2004-04-13 |
| 6704841 | Method and apparatus for facilitating speculative stores in a multiprocessor system | Marc Tremblay | 2004-03-09 |
| 6704862 | Method and apparatus for facilitating exception handling using a conditional trap instruction | Marc Tremblay | 2004-03-09 |
| 6701417 | Method and apparatus for supporting multiple cache line invalidations per cycle | Marc Tremblay | 2004-03-02 |
| 6684398 | Monitor entry and exit for a speculative thread during space and time dimensional execution | Marc Tremblay | 2004-01-27 |
| 6684297 | Reverse directory for facilitating accesses involving a lower-level cache | Marc Tremblay | 2004-01-27 |
| 6681318 | Method and apparatus for using an assist processor to prefetch instructions for a primary processor | Marc Tremblay | 2004-01-20 |