Issued Patents 2004
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6801997 | Multiple-thread processor with single-thread interface shared among threads | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2004-10-05 |
| RE38599 | Pipelined instruction dispatch unit in a superscalar processor | — | 2004-09-21 |
| D494812 | Cover for salt and pepper shaker | — | 2004-08-24 |
| 6772321 | Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor | Shailender Chaudhry | 2004-08-03 |
| 6757820 | Decompression bit processing with a general purpose alignment tool | Subramania Sudharsanan, Jeffrey Meng Wah Chan | 2004-06-29 |
| 6754775 | Method and apparatus for facilitating flow control during accesses to cache memory | Shailender Chaudhry | 2004-06-22 |
| 6732363 | Supporting inter-process communication through a conditional trap instruction | Shailender Chaudhry | 2004-05-04 |
| 6725308 | Locking of computer resources | William N. Joy, James M. O'Connor | 2004-04-20 |
| 6718839 | Method and apparatus for facilitating speculative loads in a multiprocessor system | Shailender Chaudhry | 2004-04-13 |
| 6721855 | Using an L2 directory to facilitate speculative loads in a multiprocessor system | Shailender Chaudhry | 2004-04-13 |
| 6721944 | Marking memory elements based upon usage of accessed information during speculative execution | Shailender Chaudhry | 2004-04-13 |
| 6718457 | Multiple-thread processor for threaded software applications | William N. Joy | 2004-04-06 |
| 6704862 | Method and apparatus for facilitating exception handling using a conditional trap instruction | Shailender Chaudhry | 2004-03-09 |
| 6704841 | Method and apparatus for facilitating speculative stores in a multiprocessor system | Shailender Chaudhry | 2004-03-09 |
| 6704822 | Arbitration protocol for a shared data cache | Andre Kowalczyk, Anup S. Tirumula | 2004-03-09 |
| 6701417 | Method and apparatus for supporting multiple cache line invalidations per cycle | Shailender Chaudhry | 2004-03-02 |
| 6694347 | Switching method in a multi-threaded processor | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2004-02-17 |
| D486553 | Watering can | — | 2004-02-10 |
| 6684398 | Monitor entry and exit for a speculative thread during space and time dimensional execution | Shailender Chaudhry | 2004-01-27 |
| 6684297 | Reverse directory for facilitating accesses involving a lower-level cache | Shailender Chaudhry | 2004-01-27 |
| 6681318 | Method and apparatus for using an assist processor to prefetch instructions for a primary processor | Shailender Chaudhry | 2004-01-20 |