PH

Peter Hsu

KT Kabushiki Kaisha Toshiba: 1 patents #648 of 2,092Top 35%
MT Mips Technologies: 1 patents #7 of 25Top 30%
Nintendo Co.: 1 patents #18 of 61Top 30%
📍 Merced, CA: #1 of 19 inventorsTop 6%
🗺 California: #3,906 of 28,370 inventorsTop 15%
Overall (2004): #46,366 of 270,089Top 20%
2
Patents 2004

Issued Patents 2004

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6691221 Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution Chandra Joshi, Paul Rodman, Monica R. Nofal 2004-02-10
6681296 Method and apparatus for software management of on-chip cache Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng 2004-01-20