Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Luiz Andre Barroso, Kourosh Gharachorloo, Robert Stets, Mosur K. Ravishankar | 2004-06-15 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Kourosh Gharachorloo | 2004-04-20 |
| 6725343 | System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system | Luiz Andre Barroso, Kourosh Gharachorloo | 2004-04-20 |
| 6697919 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar | 2004-02-24 |
| 6675265 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets | 2004-01-06 |