Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6751710 | Scalable multiprocessor system and cache coherence method | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-15 |
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Luiz Andre Barroso, Andreas Nowatzyk, Robert Stets, Mosur K. Ravishankar | 2004-06-15 |
| 6748498 | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-08 |
| 6738868 | System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes | Luiz Andre Barroso, Daniel J. Scales | 2004-05-18 |
| 6725343 | System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system | Luiz Andre Barroso, Andreas Nowatzyk | 2004-04-20 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Andreas Nowatzyk | 2004-04-20 |
| 6697919 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar, Andreas Nowatzyk | 2004-02-24 |
| 6678840 | Fault containment and error recovery in a scalable multiprocessor | Richard E. Kessler, Peter J. Bannon, Thukalan V. Verghese | 2004-01-13 |
| 6675265 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Andreas Nowatzyk, Mosur K. Ravishankar, Robert Stets | 2004-01-06 |