Issued Patents 2004
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6835654 | Methods of forming an electrically conductive line | Gurtej S. Sandhu | 2004-12-28 |
| 6822299 | Boron-doped titanium nitride layer for high aspect ratio semiconductor devices | Ammar Derraa, Paul Castrovillo | 2004-11-23 |
| 6815344 | Methods of forming an electrically conductive line | Gurtej S. Sandhu | 2004-11-09 |
| 6812512 | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture | Kirk D. Prall, Howard E. Rhodes, Gurtel Sandhu, Philip J. Ireland | 2004-11-02 |
| 6800517 | Methods of forming conductive interconnects | Gurtej S. Sandhu, Trung T. Doan, Howard E. Rhodes, Philip J. Ireland, Martin C. Roberts | 2004-10-05 |
| 6791149 | Diffusion barrier layer for semiconductor wafer fabrication | Ammar Derraa, Paul Castrovillo | 2004-09-14 |
| 6777330 | Chemistry for chemical vapor deposition of titanium containing films | Howard E. Rhodes, Philip J. Ireland, Gurtej S. Sandhu | 2004-08-17 |
| 6773502 | Method of forming a crystalline phase material | Gurtej S. Sandhu | 2004-08-10 |
| 6759306 | Methods of forming silicon dioxide layers and methods of forming trench isolation regions | Gurtej S. Sandhu | 2004-07-06 |
| 6756088 | Methods of forming coatings on gas-dispersion fixtures in chemical-vapor-deposition systems | — | 2004-06-29 |
| 6756293 | Combined gate cap or digit line and spacer deposition using HDP | Weimin Li, Gurtej S. Sandhu | 2004-06-29 |
| 6750089 | Methods of forming conductive interconnects | Gurtej S. Sandhu, Trung T. Doan, Howard E. Rhodes, Philip J. Ireland, Martin C. Roberts | 2004-06-15 |
| 6749717 | Device for in-situ cleaning of an inductively-coupled plasma chambers | Gurtej S. Sandhu | 2004-06-15 |
| 6746952 | Diffusion barrier layer for semiconductor wafer fabrication | Ammar Derraa, Paul Castrovillo | 2004-06-08 |
| 6737328 | Methods of forming silicon dioxide layers, and methods of forming trench isolation regions | Gurtej S. Sandhu | 2004-05-18 |
| 6727173 | Semiconductor processing methods of forming an utilizing antireflective material layers, and methods of forming transistor gate stacks | Gurtej S. Sandhu | 2004-04-27 |
| 6706116 | Method of forming a crystalline phase material | Gurtej S. Sandhu | 2004-03-16 |
| 6706158 | Electrochemical mechanical planarization | — | 2004-03-16 |
| 6705246 | RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition | Gurtej S. Sandhu, Paul Smith, Mei Chang | 2004-03-16 |
| 6696368 | Titanium boronitride layer for high aspect ratio semiconductor devices | Ammar Derraa, Paul Castrovillo | 2004-02-24 |
| 6686288 | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture | Kirk D. Prall, Howard E. Rhodes, Gurtel Sandhu, Philip J. Ireland | 2004-02-03 |