Issued Patents 2004
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6820181 | Method and system for controlling memory accesses to memory modules having a memory hub architecture | Terry R. Lee | 2004-11-16 |
| 6789169 | Embedded DRAM cache memory and method having reduced latency | — | 2004-09-07 |
| 6789168 | Embedded DRAM cache | — | 2004-09-07 |
| 6789155 | System and method for controlling multi-bank embedded DRAM | — | 2004-09-07 |
| 6754117 | System and method for self-testing and repair of memory modules | — | 2004-06-22 |
| 6745309 | Pipelined memory controller | — | 2004-06-01 |
| 6742074 | Bus to system memory delayed read processing | — | 2004-05-25 |
| 6741254 | Method of implementing an accelerated graphics port for a multiple memory controller computer system | — | 2004-05-25 |
| 6735709 | Method of timing calibration using slower data rate pattern | Terry R. Lee, Kevin J. Ryan | 2004-05-11 |
| 6717582 | Accelerated graphics port for a multiple memory controller computer system | — | 2004-04-06 |
| 6684304 | Method to access memory based on a programmable page limit | — | 2004-01-27 |