DL

Dawn M. Lee

Lsi Logic: 1 patents #184 of 528Top 35%
📍 San Jose, CA: #938 of 2,805 inventorsTop 35%
🗺 California: #8,555 of 28,370 inventorsTop 35%
Overall (2004): #238,628 of 270,089Top 90%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6713394 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Ronald J. Nagahara, Jayanthi Pallinti 2004-03-30