Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810505 | Integrated circuit design flow with capacitive margin | Maad Al-Dabagh, Duc Huynh, Ruben Molina | 2004-10-26 |
| 6725389 | Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit | Rajiv Kapur | 2004-04-20 |