Issued Patents 2004
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6831866 | Method and apparatus for read bitline clamping for gain cell DRAM devices | — | 2004-12-14 |
| 6829682 | Destructive read architecture for dynamic random access memories | Sang Hoo Dhong, Hwa-Joon Oh, Matthew R. Wordeman | 2004-12-07 |
| 6801980 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Chorng-Lii Hwang, Seiji Munetoh | 2004-10-05 |
| 6799290 | Data path calibration and testing mode using a data bus for semiconductor memories | Gerhard Mueller, David R. Hanson | 2004-09-28 |
| 6768692 | Multiple subarray DRAM having a single shared sense amplifier | Wing K. Luk | 2004-07-27 |
| 6751151 | Ultra high-speed DDP-SRAM cache | Louis L. Hsu, Li-Kong Wang, Robert C. Wong | 2004-06-15 |
| 6751152 | Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage | Louis L. Hsu, Daniel W. Storaska | 2004-06-15 |
| 6747890 | Gain cell structure with deep trench capacitor | Subramanian S. Iyer, John W. Golz | 2004-06-08 |
| 6690198 | Repeater with reduced power consumption | Gerhard Mueller | 2004-02-10 |
| 6683486 | Low voltage shifter with latching function | David R. Hanson, Gerhard Mueller | 2004-01-27 |
| 6680857 | Unit-architecture with implemented limited bank-column-select repairability | Gerhard Mueller | 2004-01-20 |
| 6674676 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Chorng-Lii Hwang, Dale E. Pontius | 2004-01-06 |
| 6674673 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Chorng-Lii Hwang, Dale E. Pontius | 2004-01-06 |