RA

R. Dean Adams

CS Cadence Design Systems: 1 patents #23 of 106Top 25%
📍 South Burlington, VT: #61 of 166 inventorsTop 40%
🗺 Vermont: #171 of 538 inventorsTop 35%
Overall (2004): #135,688 of 270,089Top 55%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6681350 Method and apparatus for testing memory cells for data retention faults Aneesha P. Deo, Kamran Zarrineh 2004-01-20