Issued Patents 2004
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6799309 | Method for optimizing a VLSI floor planner using a path based hyper-edge representation | Nagashyamala R. Dhanwada, Glenn E. Holmes, Joseph Morrell, Natesan Venkateswaran | 2004-09-28 |