Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6799309 | Method for optimizing a VLSI floor planner using a path based hyper-edge representation | Nagashyamala R. Dhanwada, Joseph Morrell, Jose L. Neves, Natesan Venkateswaran | 2004-09-28 |
| 6748565 | System and method for adjusting timing parts | Timothy G. McNamara, William J. Scarpero, Jr. | 2004-06-08 |