Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825711 | Power reduction by stage in integrated circuit | John M. Cohn, Kenneth J. Goodnow, Scott Whitney Gould, Sebastian T. Ventrone | 2004-11-30 |
| 6820240 | Voltage island chip implementation | Thomas R. Bednar, Scott Whitney Gould, David E. Lackey, Paul S. Zuchowski | 2004-11-16 |
| 6779163 | Voltage island design planning | Thomas R. Bednar, Scott Whitney Gould, David E. Lackey, Paul S. Zuchowski | 2004-08-17 |
| 6731154 | Global voltage buffer for voltage islands | Thomas R. Bednar, Scott Whitney Gould, David E. Lackey, Paul S. Zuchowski | 2004-05-04 |
| 6725439 | Method of automated design and checking for ESD robustness | Philip S. Homsinger, Andrew D. Huber, Debra K. Korejwa, William J. Livingstone, Jeannie H. Panner +3 more | 2004-04-20 |